Using TimingTool On-line is FREE

Why it TimingTool On-line useage free?

TimingTool On-line applet is always going to be free to all users. TimingTool On-line is always available; this is NOT a demonstration version although some features are unavailable due to the inherent nature of applets. TimingTool On-line does however require a connection to the Internet and can only access your personal on-line work area. It cannot be downloaded.

TimingTool On-line is a fully featured timing diagram editing software that gives you the capability to draw Timing Diagrams on-line and output your diagrams for documentation.

These features are usually only available with expensive editing software. So please make use of TimingTool On-line, and promote its features to other engineers, students and colleagues.

Inevitably, we have received many requests to purchase an application version of TimingTool. In response, TimingTool is now available in 2 variants:

1. Full application version of TimingTool that can be downloaded. The application version of TimingTool is a major enhancement over TimingTool On-line with a great many features.

   • Full timing diagram annotation (setup, hold, delay etc).
   • Parameter tables.
   • Dynamic timing diagrams with parameter linked constraints, highlighting in red to indicate violations.
   • Export capability from the parameter table to Excel, CSV, or HTML.
   • Full rendering of relationships in real time.
   • Excellent documentation outputs including: HTML, Postscript, PNG, JPEG, and BMP.
   • Web Publishing of timing diagrams to an intranet or direct to the web for on-line access to IP datasheets.
   • Complete Macro Language (Javabeans) - gives the user the capability to control any aspect of TimingTool. Ideal for reading or writing proprietary timing information into or out of TimingTool. The Macro Language is also perfect for automatically deriving one signal from an other(s). Allows TimingTool to be tailored to your organisations exact requirements.
   • Imports VHDL and Verilog automatically generating signals.
   • Automatically generate VHDL and Verilog test benches from your timing diagrams.


2. Full application version of TimingTool without HDL Testbench Generation.
   • This option is available at a lower price than the full version of TimingTool and is suitable for users that do not require HDL Testbench generation.